As a preliminary matter, this invention concerns circuits that use voltages to represent binary logic values. Particular circuits may use varying voltage levels to represent the two binary logic values. Accordingly, the words "high" and "low" in this specification refer generally to voltages corresponding to the true and false binary logic values, respectively, within a given sub-circuit. Signals are generally considered "active" when they are high. However, a "*" following the signal name indicates that the signal has negative or inverse logic: the signal is considered active when low. These conventions will be used in the following written discussion. In the drawings, negative logic signals are indicated with a bar over the signal name.
Dual-port RAMs, commonly referred to as video RAMs or VRAMs, offer dramatic speed improvements over standard dynamic RAMs (DRAMs). VRAMs are particularly effective in video display systems and in other applications where high-speed data buffering is required.
A VRAM has an array of dynamic memory cells or registers. The array is accessed through either conventional DRAM control signals or through a serial access memory (SAM). A SAM is essentially a long shift register which receives a block of data from the dynamic memory array and shifts the data out serially through a "serial" port.
VRAMs are particularly useful as frame buffers for video systems. In such video systems, a graphics processor supplies randomly-addressed display frame data to a VRAM memory array as it would to conventional DRAM. The VRAM supplies a serial stream of sequentially-addressed display frame data to color lookup tables and digital-to-analog converters. The serial transfer does not interfere with the graphics processor's random access of the VRAM memory array.
VRAMs and their applications in video systems are well-known. For instance, Micron Technology, Inc., distributes a "1991 MOS Data Book," of which section 3 is hereby incorporated by reference, containing detailed descriptions of Micron's line of VRAMs.
Various features have been incorporated in VRAMs to speed data transfer to and from an associated graphics processor or microprocessor. An article published in Electronic Design, Nov. 23, 1989, entitled "Speed Memory, Ease Timing Requirements With VRAM Functions," by Mailloux, et al., describes many of these features, and is also incorporated by reference.
A "block write" function is an example of a feature provided in VRAMs to enhance speed of memory writing. The block write function is useful in a VRAM video frame buffer to quickly clear a large area of frame buffer memory or to create a background for a display window. Instead of writing to just one register the block write function allows simultaneous writing to a block of memory registers. Such a block may comprise an arbitrary or predefined number of memory registers or a logical unit of memory registers such as an entire row of memory registers.
Two types of block write functions are discussed in the following specification. The term "block writing" refers generally to both. The first type of block write function, referred to herein as a "selective block write," allows simultaneous writing to a selected block of four memory registers within a single row of memory registers. The second type of block write function, referred to herein as a "flash block write," allows simultaneous writing to an entire row of memory registers.
The selective block write and flash block write functions may also be used in conjunction with other VRAM features such as the masked write functions described below.
FIG. 1 is a block diagram of a prior art VRAM circuit, designated by the reference numeral 10, which includes both types of block write functions. Additional circuits and signals, not shown, are of course necessary to the operation of VRAM 10, as those familiar with this technology will recognize. Such circuits and signals are omitted here for the sake of simplicity, and to focus the reader's attention on VRAM elements which relate more specifically to the invention.
VRAM 10 comprises dynamic random access memory (DRAM) circuits similar in structure and function to those found in conventional DRAM devices, such as referred to in Section 1 of Micron's 1991 MOS Data Book. A DRAM array 12 in VRAM 10 comprises an array of dynamic memory cells forming eight-bit memory registers for storing binary-coded data. DRAM array 12 is arranged logically as eight planes, each plane having addressed rows and columns of memory cells. Each eight-bit memory register is made up of memory cells from the eight planes having the same row and column addresses. DRAM array 12 thus forms addressed rows and columns of eight-bit memory registers.
A microprocessor (not shown) accesses VRAM 10 through a data bus 14, a multiplexed address bus 16, row and column address strobe signals RAS* and CAS*, a special function signal DSF, a mask enable/write enable signal ME*/WE*, and by using other conventional control signals which are not shown. Address bus 16 receives individual address signals A0 through A8 from the microprocessor. Data bus 14 produces and receives individual data signals DQ1 through DQ8.
A row address latch/buffer 20 and a row decoder 22 receive a row address signal from multiplexed address bus 16, decode a row address therefrom, and address or activate the corresponding row of DRAM array 12. A column address latch/buffer 24 and a column decoder 26 receive a column address signal from address bus 16, decode a column address therefrom, and address or activate the corresponding column of DRAM array 12. During block write cycles, column decoder 26 simultaneously addresses and writes to a block of memory registers comprising either an entire addressed row of memory registers or a consecutively-addressed block of four memory registers within an addressed row.
Data bus 14 receives memory register data during a write cycle from the microprocessor and supplies it to column decoder 26 for writing to DRAM array 12. Column decoder 26 produces memory register data from DRAM array 12 at data bus 14 during read cycles.
A write register 34 receives data from data bus 14 during write register load cycles. Write register 34 supplies block write data to column decoder 26. A bit masking circuit 55 and a column masking circuit 56 receive mask data from data bus 14 as will be explained more fully below with reference to FIG. 2. Bit masking circuit 55 and column masking circuit 56 supply mask data to column decoder 26 through a decoder logic circuit 57.
VRAM 10 includes a serial access memory or SAM 36. SAM 36 is a single row of eight-bit memory registers, with columns corresponding to the columns of DRAM array 12. SAM 36, when appropriately activated, simultaneously transfers data between its memory registers and the memory registers of a row of DRAM array 12.
A SAM address counter 38 is associated with SAM 36 to generate sequential SAM column addresses. A SAM decoder 40 receives the generated addresses. SAM decoder 40 has a serial data bus 41 connected to produce and receive serial data signals SDQ1 through SDQ8. SAM decoder 40 is responsive to the sequential SAM column addresses from SAM address counter 38 to transfer data between the corresponding column of SAM 36 and serial data bus 41. A SAM address latch/buffer 42 receives a beginning SAM column address signal from address bus 16 and initializes SAM address counter 38 accordingly.
Various additional control circuits and signals initiate and synchronize VRAM operations. However, since this invention is concerned primarily with the block write functions of VRAM 10, and since VRAM circuits and operational details are well documented, they are not described further here. Reference may be made to the data sheets and specifications previously mentioned regarding VRAMs for a more detailed description of timing and control requirements, including control signal requirements for transferring data into SAM 36 from DRAM array 12 and for serially transferring such data out through SAM decoder 40.
FIG. 2 is provided to simplify the explanation of the selective block write function in VRAM 10. FIG. 2 is thus a conceptual diagram of the selective block write function, rather than a representation of physical elements within VRAM 10.
DRAM array 12 is shown as eight two-dimensional planes of memory cells. Together, the planes form rows and columns of eight-bit memory registers as already described. Individual memory cells are not shown, with the exception of an arbitrarily selected block of four consecutively-addressed memory cells 52 in each plane. Memory cells 52 are shown as an example of addressing during a selective block write cycle.
Write register 34 is an eight-bit static memory register. In a typical selective block write application, write register 34 is first initialized during a write register load cycle. Subsequently, data from write register 34 is written to blocks of memory registers within DRAM array 12, such as block 52, during block write cycles.
During a selective block write cycle, a row address and a column address are provided to VRAM 10 through multiplexed address bus 16. VRAM 10 latches the row address from A0 through A8 at the falling edge of RAS*, and the column address from A2 through A8 at the falling edge of CAS*, similar to a normal write cycle. A0 and A1 of the column address are disregarded during the selective block write cycle. The row address and column block address form a memory register base address which is the address of the first memory register of a block of four adjacent memory registers within a row. Memory cells 52 are shown in FIG. 2, in each of the logical planes of DRAM array 12, as an example of four adjacent memory registers within a row being simultaneously addressed for writing during a selective block write cycle.
Data is then written simultaneously from write register 34 to the block of adjacent memory registers through bit masking circuit 55 and column masking circuit 58. Data is not written from data bus 14.
Bit masking circuit 55 allows individual bits to be masked from writing so that a memory write may be performed on specified bits without altering the remaining bits. Bit masking circuit 55 contains a bit mask register 61 and eight corresponding bit enable gates 59. Bit mask register 61 is loaded with a bit mask code from data signals DQ1 through DQ8 during a bit mask register load cycle. Each bit of bit mask register 61 corresponds to a bit of write register 34. A bit value of zero indicates that the corresponding write register bit is to be masked. A bit value of one indicates that the corresponding write register bit is to be written to DRAM array 12.
Column or register masking circuit 56 allows specification of a column of register mask code. The column mask code is latched in a column mask register 60 from data signals DQ1 through DQ4 at the latter of WE* and CAS* going low during the selective block write cycle. Each bit of column mask register 60 corresponds to one of the four adjacent column locations. A bit value of zero indicates that the corresponding column is to be masked. A bit value of one indicates that the corresponding column is to be written from write register 34.
FIG. 3 a conceptual diagram of the flash block write function. A flash write is very similar to a block write, except that an entire row of memory registers is selected and written to simultaneously.
As in a selective block write cycle, write register 34 is first initialized during a write register load cycle. Subsequently, data from write register 34 is written to rows of memory registers within DRAM array 12.
Write register 34 provides an eight-bit data word during flash write cycles. The eight bits are routed through bit masking circuit 55 before being supplied to DRAM array 12. A row address is provided to VRAM 10 through multiplexed address bus 16. VRAM 10 latches the row address from A0 through A8 at the falling edge of RAS*. Memory register row 53 is shown in FIG. 3, in each of the logical planes of DRAM array 12, as an example of a register row being simultaneously addressed for writing during a flash write cycle.
Bit masking circuit 55 functions during a flash block write cycle as already described above to mask individual bits in each memory register from being written.
As a background, FIG. 4 illustrates the required sequence and relative timing of control signals to perform a normal write cycle to a single memory register within DRAM 12. DSF remains low throughout the entire write cycle. RAS* goes low to signal the presence of a valid row address signal at A0 through A8. ME*/WE* and CAS* go low to signal a valid column address at A0 through A8. At the latter of ME*/WE* and CAS* going low the data on DQ1 through DQ8 is written to the addressed memory register.
FIG. 5 illustrates the required sequence and relative timing of control signals to perform a write register load cycle, wherein write register 34 (FIGS. 1-3) is loaded from DQ1 through DQ8. The write register load cycle is similar to a normal write cycle, with address signals A0 through A8 being "don't cares," since there is no need to specify a memory address. DSF and ME*/WE* are both high as RAS* goes low to signal initiation of the write register load cycle. CAS* is lowered during the write register load cycle to indicate the presence of valid write register data at DQ1 through DQ8. DSF must remain high throughout the write register load cycle.
FIG. 6 illustrates the required sequence and relative timing of control signals to load bit mask register 61. This sequence is similar to a load write register cycle, except that DSF must be low when CAS* goes low. The bit mask register data is loaded from DQ1 through DQ8 at the falling edge of CAS*. Address signals A0 through A8 are "don't cares," since there is no need to specify a memory address. DSF and ME*/WE* are both high as RAS* goes low to signal initiation of the write register load cycle.
FIG. 7 illustrates the required sequence and relative timing of control signals to perform a selective block write cycle, wherein a block of four consecutively-addressed memory registers within a row of DRAM array 12 are simultaneously written with data from write register 34. As RAS* goes low, ME*/WE* is high and DSF is low to signal initiation of a selective block write cycle. DSF additionally must be high as CAS* goes low. RAS* going low also signals to VRAM 10 the presence of a valid row address at A0 through A8. ME*/WE* and CAS* are lowered to signal the presence of a valid column block address at A2 through A8. The contents of write register 34 are written to the addressed block of memory registers at the latter of CAS* and ME*/WE* to go low. A0 and A1 are ignored in forming the column block address during a selective block write cycle. A column mask code must be presented at DQ1 through DQ4 as CAS* goes low. DQ5 through DQ8 are unused during selective block write cycles.
FIG. 8 illustrates the required sequence and relative timing of control signals to perform a flash block write cycle in VRAM 10, wherein an entire row of memory registers within DRAM array 12 are simultaneously written with data from write register 34. As RAS* goes low, ME*/WE* is high and DSF is high to signal initiation of the flash write cycle. RAS* going low also signals to VRAM 10 the presence of a valid row address at A0 through A8. As ME*/WE* and CAS* are lowered, a column mask code is presented by data signals DQ1 through DQ4. Additionally, a column block address is presented by data signals A2 through A8 as ME*/WE* and CAS* go low. At the latter of CAS* and ME*/WE* to fall, data is written from the selected write register to the selected row of memory registers.
DRAMs and VRAMs typically incorporate, in addition to the block write functions, other functions which speed writing and reading of memory registers, such as a page writing and static column addressing. The invention described below, however, is concerned with providing an enhancement to block writing, wherein data may be written during a block write cycle from a selected one of several write registers. Such an enhancement speeds memory operations by eliminating the need to perform a write register load cycle when it is desired to change the value written during block write cycles. Data may be preloaded in a plurality of write registers and an individual write register selected during the block write cycle itself.